🔬 Flip-Flop Virtual Laboratory

Interactive Digital Sequential Logic Laboratory
ACTIVE EXPERIMENT: SR FLIP-FLOP
PRIMARY:
MODE & CONTROL:
🎛️ INPUT CONTROLS RISING EDGE
Data Inputs
S Set Input (Forces Q = 1)
R Reset Input (Forces Q = 0)

ℹ️ Inputs sample strictly on the Rising Clock Edge (↑).

CLK Generator STOPPED
HIGH (1) LOW (0)
Speed: 1.2s
📐 INTERNAL LOGIC Gate-Level View
S CLK R Q Q̅ NAND1 NAND2 NAND3 NAND4
📊 STATE & OUTPUT HOLD
CURRENT STORED STATE Q = 0, Q̅ = 1 State: RESET / LOGIC 0
CURRENT OPERATION / CLOCK EXPECTATION No change. The Flip-Flop retains its previous state.
S=0, R=0 ➔ HOLD ➔ CLK ↑ ➔ Q=0
PREVIOUS Q 0
NEXT Q 0
Outputs
Q LOGIC 0
Q̅ LOGIC 1
⚠️

FORBIDDEN / INVALID INPUT CONDITION (S = 1, R = 1)

Both NAND gates attempt to force outputs LOW (Q = Q̅ = 0), causing race conditions on clock release.

💡

WHAT IS HAPPENING?

S=0 and R=0. The Flip-Flop is in HOLD condition and will retain its current state on the next clock edge.

📋 SR Flip-Flop Truth Table ACTIVE ROW HIGHLIGHTED
CLKSRQ(next)Operation
↑00Q(previous)HOLD
↑010RESET
↑101SET
↑11INVALIDFORBIDDEN
📜 State Transition Log
ClockInputsOperationTransitionResult
#00S=0 R=0INITIAL0 → 0Q=0
🎛️ INPUT CONTROLS RISING EDGE
Data Inputs
J Set / Toggle Input
K Reset / Toggle Input

ℹ️ Inputs sample strictly on the Rising Clock Edge (↑).

CLK Generator STOPPED
HIGH (1) LOW (0)
Speed: 1.2s
📐 INTERNAL LOGIC Gate-Level View
J CLK K Q Q̅ NAND1 NAND2 NAND3 NAND4
📊 STATE & OUTPUT HOLD
CURRENT STORED STATE Q = 0, Q̅ = 1 State: RESET / LOGIC 0
CURRENT OPERATION / CLOCK EXPECTATION The Flip-Flop retains its previous state.
J=0, K=0 ➔ HOLD ➔ CLK ↑ ➔ Q=0
PREVIOUS Q 0
NEXT Q 0
Outputs
Q LOGIC 0
Q̅ LOGIC 1
⚡

TOGGLE MODE ACTIVE (J = 1, K = 1)

When J = 1 and K = 1, each rising clock edge (↑) inverts stored output state Q (Qnext = NOT Qprev).

💡

WHAT IS HAPPENING?

J=0 and K=0. The Flip-Flop is in HOLD condition and will retain its current state on the next clock edge.

📋 JK Flip-Flop Truth Table ACTIVE ROW HIGHLIGHTED
CLKJKQ(previous)Q(next)Operation
↑0000HOLD
↑0011HOLD
↑0100RESET
↑0110RESET
↑1001SET
↑1011SET
↑1101TOGGLE
↑1110TOGGLE
📜 State Transition Log
ClockInputsOperationTransitionResult
#00J=0 K=0INITIAL0 → 0Q=0
🎛️ INPUT CONTROLS RISING EDGE
Data Input
D Data Input (Q(next) = D)

ℹ️ Inputs sample strictly on the Rising Clock Edge (↑).

CLK Generator STOPPED
HIGH (1) LOW (0)
Speed: 1.2s
📐 INTERNAL LOGIC Gate-Level View
D CLK Q Q̅ NAND1 NAND2 NAND3 NAND4
📊 STATE & OUTPUT STORE 0
CURRENT STORED STATE Q = 0, Q̅ = 1 State: RESET / LOGIC 0
CURRENT OPERATION / CLOCK EXPECTATION The Flip-Flop will store Logic 0 on the next rising clock edge.
D=0 ➔ STORE 0 ➔ CLK ↑ ➔ Q=0
PREVIOUS Q 0
NEXT Q 0
Outputs
Q LOGIC 0
Q̅ LOGIC 1
💡

WHAT IS HAPPENING?

D=0. The Flip-Flop will store Logic 0 at the next rising clock edge.

📋 D Flip-Flop Truth Table ACTIVE ROW HIGHLIGHTED
CLKDQ(previous)Q(next)Operation
↑000STORE 0
↑010STORE 0
↑101STORE 1
↑111STORE 1
📜 State Transition Log
ClockInputsOperationTransitionResult
#00D=0INITIAL0 → 0Q=0
🎛️ INPUT CONTROLS RISING EDGE
Toggle Input
T Toggle Input (Inverts Q on CLK)

ℹ️ Inputs sample strictly on the Rising Clock Edge (↑).

CLK Generator STOPPED
HIGH (1) LOW (0)
Speed: 1.2s
📐 INTERNAL LOGIC Gate-Level View
T CLK Q Q̅ NAND1 NAND2 NAND3 NAND4
📊 STATE & OUTPUT HOLD
CURRENT STORED STATE Q = 0, Q̅ = 1 State: RESET / LOGIC 0
CURRENT OPERATION / CLOCK EXPECTATION The Flip-Flop retains its previous state.
T=0 ➔ HOLD ➔ CLK ↑ ➔ Q=0
PREVIOUS Q 0
NEXT Q 0
Outputs
Q LOGIC 0
Q̅ LOGIC 1
💡

WHAT IS HAPPENING?

T=0. The Flip-Flop is in HOLD condition and will retain its current state on the next clock edge.

📋 T Flip-Flop Truth Table ACTIVE ROW HIGHLIGHTED
CLKTQ(previous)Q(next)Operation
↑000HOLD
↑011HOLD
↑101TOGGLE
↑110TOGGLE
📜 State Transition Log
ClockInputsOperationTransitionResult
#00T=0INITIAL0 → 0Q=0
🔬 Sequential Logic — Flip-Flop Family Comparison Matrix Comparison Table
Flip-Flop Inputs HOLD Condition SET Condition RESET Condition TOGGLE Condition
SR S, R S=0, R=0 S=1, R=0 S=0, R=1 INVALID (11)
JK J, K J=0, K=0 J=1, K=0 J=0, K=1 J=1, K=1
D D — D=1 D=0 —
T T T=0 — — T=1
📚 LEARN THE CONCEPT Theory Guide

🧠 Working Principle

Sequential logic circuits utilize feedback loops to store binary state information. A Flip-Flop updates its output state Q strictly on the Rising Edge (↑) of a clock pulse.

📋 Truth Table

Truth tables define state outputs (Q(next)) for all input combinations at active clock transitions. Inputs remain latched until the next clock cycle.

⚙️ Characteristic Equations

Algebraic representations of flip-flop state transitions:

  • SR: Q(next) = S + R̅Q
  • JK: Q(next) = J Q̅ + K̅ Q
  • D: Q(next) = D
  • T: Q(next) = T ⊕ Q

🚀 Applications

Primary building blocks for registers, memory cells, binary ripple counters, frequency dividers, and synchronous state controllers.